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| Main Authors: | , , , , , , , |
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| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2412.18642 |
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| _version_ | 1866916541922017280 |
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| author | Liang, Zehong Yan, Xiongbo Ning, Zhe Hu, Jun Jiang, Xiaoshan Sun, Yunhua Pan, Weiyan Ye, Jingbo |
| author_facet | Liang, Zehong Yan, Xiongbo Ning, Zhe Hu, Jun Jiang, Xiaoshan Sun, Yunhua Pan, Weiyan Ye, Jingbo |
| contents | We have developed a Time-to-Digital Converter (TDC) application in a Xilinx Kintex-7 Field Programmable Gate Array (FPGA). This TDC, based on the Tapped-Delay Line (TDL) and Wave Union A (WU-A) techniques, achieves an independent time measurement on 32-channel rising edges and 32-channel falling edges. The average time resolution or the Least Significant Bit (LSB) of the 64 channels is measured to be 3 ps level, with an average root mean square (RMS) precision of 4.77 ps, and a maximum RMS below 8 ps. We also propose an online processing scheme that handles the bubble issues caused by clock region skew. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2412_18642 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | A 64-Channel Precision Time-to-Digital Converter with Average 4.77 ps RMS Implemented in a 28 nm FPGA Liang, Zehong Yan, Xiongbo Ning, Zhe Hu, Jun Jiang, Xiaoshan Sun, Yunhua Pan, Weiyan Ye, Jingbo Instrumentation and Detectors High Energy Physics - Experiment We have developed a Time-to-Digital Converter (TDC) application in a Xilinx Kintex-7 Field Programmable Gate Array (FPGA). This TDC, based on the Tapped-Delay Line (TDL) and Wave Union A (WU-A) techniques, achieves an independent time measurement on 32-channel rising edges and 32-channel falling edges. The average time resolution or the Least Significant Bit (LSB) of the 64 channels is measured to be 3 ps level, with an average root mean square (RMS) precision of 4.77 ps, and a maximum RMS below 8 ps. We also propose an online processing scheme that handles the bubble issues caused by clock region skew. |
| title | A 64-Channel Precision Time-to-Digital Converter with Average 4.77 ps RMS Implemented in a 28 nm FPGA |
| topic | Instrumentation and Detectors High Energy Physics - Experiment |
| url | https://arxiv.org/abs/2412.18642 |