APA (7th ed.) Citation

Taka, E., Huang, N., Chang, C., Wu, K., Arora, A., & Marculescu, D. (2025). Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration.

Chicago Style (17th ed.) Citation

Taka, Endri, Ning-Chi Huang, Chi-Chih Chang, Kai-Chiang Wu, Aman Arora, and Diana Marculescu. Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration. 2025.

MLA (9th ed.) Citation

Taka, Endri, et al. Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration. 2025.