APA (7th ed.) Citation

Nakano, H., Blachut, K., Jeziorek, K., Wzorek, P., Dampfhoffer, M., Mesquida, T., . . . Dalgaty, T. (2025). Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA.

Chicago Style (17th ed.) Citation

Nakano, Hiroshi, Krzysztof Blachut, Kamil Jeziorek, Piotr Wzorek, Manon Dampfhoffer, Thomas Mesquida, Hiroaki Nishi, Tomasz Kryjak, and Thomas Dalgaty. Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA. 2025.

MLA (9th ed.) Citation

Nakano, Hiroshi, et al. Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA. 2025.