Citazione Stile APA (7a Edizione)

Vieira, J. V. A., Gomes, L. d. M., Sumitani, R., Maciel, R., Mafra, A., Crepalde, M., & Pereira, F. M. Q. (2025). Bottom-Up Generation of Verilog Designs for Testing EDA Tools.

Citazione stile Chigago Style (17a edizione)

Vieira, João Victor Amorim, Luiza de Melo Gomes, Rafael Sumitani, Raissa Maciel, Augusto Mafra, Mirlaine Crepalde, e Fernando Magno Quintão Pereira. Bottom-Up Generation of Verilog Designs for Testing EDA Tools. 2025.

Citatione MLA (9a ed.)

Vieira, João Victor Amorim, et al. Bottom-Up Generation of Verilog Designs for Testing EDA Tools. 2025.