Style de citation APA (7e éd.)

Han, Z., Qian, Y., Zink, M., & Leeser, M. (2025). Memory-efficient Sketch Acceleration for Handling Large Network Flows on FPGAs.

Style de citation Chicago (17e éd.)

Han, Zhaoyang, Yicheng Qian, Michael Zink, et Miriam Leeser. Memory-efficient Sketch Acceleration for Handling Large Network Flows on FPGAs. 2025.

Style de citation MLA (9e éd.)

Han, Zhaoyang, et al. Memory-efficient Sketch Acceleration for Handling Large Network Flows on FPGAs. 2025.