Cita APA (7a ed.)

Wang, N., Yao, B., Zhou, J., Hu, Y., Wang, X., Guan, N., & Jiang, Z. (2025). VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction.

Cita Chicago Style (17a ed.)

Wang, Ning, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Nan Guan, y Zhe Jiang. VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction. 2025.

Cita MLA (9a ed.)

Wang, Ning, et al. VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction. 2025.