APA (7th ed.) Citation

Hemadri, R. V., Bhandari, J., Nakkab, A., Knechtel, J., Gopalan, B. P., Narayanaswamy, R., . . . Garg, S. (2025). VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code.

Chicago Style (17th ed.) Citation

Hemadri, Raghu Vamshi, Jitendra Bhandari, Andre Nakkab, Johann Knechtel, Badri P. Gopalan, Ramesh Narayanaswamy, Ramesh Karri, and Siddharth Garg. VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code. 2025.

MLA (9th ed.) Citation

Hemadri, Raghu Vamshi, et al. VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code. 2025.