Wafer-scale High-k SrTiO3 Dielectrics with Rational Barrier-layer Design for Low Leakage and High Charge Density
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arXiv
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| Autori principali: | , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2026
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| _version_ | 1866914234912210944 |
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| author | Mohseni, Majid Varshney, Shivasheesh Jeong, Seung Gyo Walton, Amber Frisbie, C. Daniel Jalan, Bharat |
| author_facet | Mohseni, Majid Varshney, Shivasheesh Jeong, Seung Gyo Walton, Amber Frisbie, C. Daniel Jalan, Bharat |
| contents | High-k oxides such as SrTiO3 promise large capacitance, but their dielectric response is often limited by leakage currents due to reduced bandgaps. We show that introducing a thin barrier layer beneath SrTiO3 is a simple and effective way to suppress leakage and increase charge density. Using hybrid molecular beam epitaxy, we grew uniform SrTiO3 films on Nb:SrTiO3, CaSnO3/Nb:SrTiO3, and 2-inch SiO2/p-Si stacks to directly compare how different barrier layers influence device behavior. Both CaSnO3 and SiO2 reduce leakage, but the ultra-wide-bandgap SiO2 layer enables much higher operating voltages, yielding charge densities exceeding 5x10^13 cm^-2 at room temperature - more than a fivefold enhancement compared to devices without a barrier layer. This improvement comes with a predictable trade-off: the lower dielectric constant of SiO2 reduces overall capacitance, making its thickness an important design parameter. Together, these results demonstrate that rational barrier-layer engineering - including wafer-scale integration on Si - provides a clear pathway to achieving higher charge densities in SrTiO3-based dielectric devices. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2601_02619 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | Wafer-scale High-k SrTiO3 Dielectrics with Rational Barrier-layer Design for Low Leakage and High Charge Density Mohseni, Majid Varshney, Shivasheesh Jeong, Seung Gyo Walton, Amber Frisbie, C. Daniel Jalan, Bharat Materials Science High-k oxides such as SrTiO3 promise large capacitance, but their dielectric response is often limited by leakage currents due to reduced bandgaps. We show that introducing a thin barrier layer beneath SrTiO3 is a simple and effective way to suppress leakage and increase charge density. Using hybrid molecular beam epitaxy, we grew uniform SrTiO3 films on Nb:SrTiO3, CaSnO3/Nb:SrTiO3, and 2-inch SiO2/p-Si stacks to directly compare how different barrier layers influence device behavior. Both CaSnO3 and SiO2 reduce leakage, but the ultra-wide-bandgap SiO2 layer enables much higher operating voltages, yielding charge densities exceeding 5x10^13 cm^-2 at room temperature - more than a fivefold enhancement compared to devices without a barrier layer. This improvement comes with a predictable trade-off: the lower dielectric constant of SiO2 reduces overall capacitance, making its thickness an important design parameter. Together, these results demonstrate that rational barrier-layer engineering - including wafer-scale integration on Si - provides a clear pathway to achieving higher charge densities in SrTiO3-based dielectric devices. |
| title | Wafer-scale High-k SrTiO3 Dielectrics with Rational Barrier-layer Design for Low Leakage and High Charge Density |
| topic | Materials Science |
| url | https://arxiv.org/abs/2601.02619 |