APA (7th ed.) Citation

Liu, Y., Ullah, S., & Kumar, A. (2026). Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators.

Chicago Style (17th ed.) Citation

Liu, Yuhao, Salim Ullah, and Akash Kumar. Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators. 2026.

MLA (9th ed.) Citation

Liu, Yuhao, et al. Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators. 2026.