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| Hauptverfasser: | , , , , , , , , |
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| Format: | Preprint |
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2026
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| Online-Zugang: | https://arxiv.org/abs/2605.01836 |
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| _version_ | 1866913084498509824 |
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| author | Yin, Shuo Liu, Fangzhou Zou, Lancheng Fu, Rongliang Zhao, Wenqian Bai, Chen Ho, Tsung-Yi Xie, Yuan Yu, Bei |
| author_facet | Yin, Shuo Liu, Fangzhou Zou, Lancheng Fu, Rongliang Zhao, Wenqian Bai, Chen Ho, Tsung-Yi Xie, Yuan Yu, Bei |
| contents | Modern hardware compilers increasingly rely on rich intermediate representations (IRs) to preserve optimization-relevant semantics before generating RTL code. However, one important optimization is still largely deferred to backend tools: pipeline optimization. In common RTL flows, registers are inserted by frontend heuristics or hardware designers and later adjusted by backend retiming after the design has been lowered to a much lower-level netlist representation. At that point, much of the operator-level structure originally exposed by the compiler IR has already been weakened or lost, limiting opportunities for global, compiler-level pipeline optimization.
This paper presents PipeRTL, an IR-level pipeline optimization framework for hardware compilers, instantiated in CIRCT. PipeRTL makes the legality of register relocation explicit in the IR, uses a learned timing predictor to approximate downstream delay behavior, and formulates timing-aware register relocation as a global min-cost flow problem under timing constraints. Evaluation on open-source designs under a commercial backend synthesis flow shows that PipeRTL improves downstream implementation quality on average, reducing critical-path delay, power, and area across the evaluated benchmarks, while also providing a stronger starting point for backend retiming. These results indicate that exposing pipeline optimization as an explicit compiler pass can deliver backend-meaningful gains by improving the sequential structure presented to later stages and the resulting downstream implementation quality. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2605_01836 |
| institution | arXiv |
| publishDate | 2026 |
| record_format | arxiv |
| spellingShingle | PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation Yin, Shuo Liu, Fangzhou Zou, Lancheng Fu, Rongliang Zhao, Wenqian Bai, Chen Ho, Tsung-Yi Xie, Yuan Yu, Bei Hardware Architecture Modern hardware compilers increasingly rely on rich intermediate representations (IRs) to preserve optimization-relevant semantics before generating RTL code. However, one important optimization is still largely deferred to backend tools: pipeline optimization. In common RTL flows, registers are inserted by frontend heuristics or hardware designers and later adjusted by backend retiming after the design has been lowered to a much lower-level netlist representation. At that point, much of the operator-level structure originally exposed by the compiler IR has already been weakened or lost, limiting opportunities for global, compiler-level pipeline optimization. This paper presents PipeRTL, an IR-level pipeline optimization framework for hardware compilers, instantiated in CIRCT. PipeRTL makes the legality of register relocation explicit in the IR, uses a learned timing predictor to approximate downstream delay behavior, and formulates timing-aware register relocation as a global min-cost flow problem under timing constraints. Evaluation on open-source designs under a commercial backend synthesis flow shows that PipeRTL improves downstream implementation quality on average, reducing critical-path delay, power, and area across the evaluated benchmarks, while also providing a stronger starting point for backend retiming. These results indicate that exposing pipeline optimization as an explicit compiler pass can deliver backend-meaningful gains by improving the sequential structure presented to later stages and the resulting downstream implementation quality. |
| title | PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2605.01836 |