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Main Authors: Exbrayat, Jules, Bouis, Renan, Sezestre, Elie, Balan, Viorel, Cornelis, Arnaud, Hebras, Damien, Euvrard, Catherine
Format: Preprint
Published: 2026
Subjects:
Online Access:https://arxiv.org/abs/2605.05062
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author Exbrayat, Jules
Bouis, Renan
Sezestre, Elie
Balan, Viorel
Cornelis, Arnaud
Hebras, Damien
Euvrard, Catherine
author_facet Exbrayat, Jules
Bouis, Renan
Sezestre, Elie
Balan, Viorel
Cornelis, Arnaud
Hebras, Damien
Euvrard, Catherine
contents As time-to-market is crucial in the Integrated Circuit (IC) industry, speeding up layout manufacturability verifi-cation is essential. Chemical-Mechanical Polishing (CMP) plays a vital role in IC fabrication but is significantly influenced by Layout-Dependent Effects (LDE). An accurate and efficient CMP model enables design teams to correct surface unevenness before fabrication, reducing costs and accelerating the design phase. However, existing models often rely on Density Step Height (DSH) modeling, which is time-consuming for calibration and requires substantial hardware resources for fine-grained predictions. In this paper, we propose combining the advantages of two surface analysis techniques, White Light Interfer-ometry (WLI) and Atomic Force Microscopy (AFM), to train a deep learning model. This model aims to predict full-chip post-CMP nanotopography with nanometer-scale accuracy. Our deep learning model is based on a Convolutional Neural Network (CNN) and follows a two-step pipeline. The model is trained on each technique separately, resulting in a detailed full-chip CMP model.
format Preprint
id arxiv_https___arxiv_org_abs_2605_05062
institution arXiv
publishDate 2026
record_format arxiv
spellingShingle Full-chip CMP modelling based on Fully Convolutional Network leveraging White Light Interferometry
Exbrayat, Jules
Bouis, Renan
Sezestre, Elie
Balan, Viorel
Cornelis, Arnaud
Hebras, Damien
Euvrard, Catherine
Machine Learning
As time-to-market is crucial in the Integrated Circuit (IC) industry, speeding up layout manufacturability verifi-cation is essential. Chemical-Mechanical Polishing (CMP) plays a vital role in IC fabrication but is significantly influenced by Layout-Dependent Effects (LDE). An accurate and efficient CMP model enables design teams to correct surface unevenness before fabrication, reducing costs and accelerating the design phase. However, existing models often rely on Density Step Height (DSH) modeling, which is time-consuming for calibration and requires substantial hardware resources for fine-grained predictions. In this paper, we propose combining the advantages of two surface analysis techniques, White Light Interfer-ometry (WLI) and Atomic Force Microscopy (AFM), to train a deep learning model. This model aims to predict full-chip post-CMP nanotopography with nanometer-scale accuracy. Our deep learning model is based on a Convolutional Neural Network (CNN) and follows a two-step pipeline. The model is trained on each technique separately, resulting in a detailed full-chip CMP model.
title Full-chip CMP modelling based on Fully Convolutional Network leveraging White Light Interferometry
topic Machine Learning
url https://arxiv.org/abs/2605.05062