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Main Authors: Yao, Wenlong, Li, Zhigang, Bai, Guobin, Gao, Jianfeng, Yu, Jiahan, Li, Junfeng, Wang, Xiaolei, Luo, Jun
Format: Preprint
Published: 2026
Subjects:
Online Access:https://arxiv.org/abs/2605.05667
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author Yao, Wenlong
Li, Zhigang
Bai, Guobin
Gao, Jianfeng
Yu, Jiahan
Li, Junfeng
Wang, Xiaolei
Luo, Jun
author_facet Yao, Wenlong
Li, Zhigang
Bai, Guobin
Gao, Jianfeng
Yu, Jiahan
Li, Junfeng
Wang, Xiaolei
Luo, Jun
contents Stacking multiple SiSiGe channels in advanced logic devices faces severe thermal budget accumulation, which degrades interfaces via Ge-Si interdiffusion and strain relaxation.This strategy lowers the Ge diffusion coefficient to 5.6-7% of its value at 650C (Arrhenius estimate), suppressing interdiffusion and preserving pseudomorphic strain. The 4 + 4 channel stack exhibits clear XRD satellite peaks, fully coherent strain state (reciprocal space mapping), sharp interfaces (1.5-2.6 nm transition width) and low RMS roughness (0.08 nm). Quantitative analysis from bottom to top reveals that prolonged high-temperature exposure broadens bottom interfaces and dilutes Ge concentration (from 20% to 18.5%), while the top stack maintains design targets. This work provides a process-physics understanding of thermal budget effects in multi-channel superlattices and establishes a high-quality material foundation for advanced logic devices beyond 2 nm node.
format Preprint
id arxiv_https___arxiv_org_abs_2605_05667
institution arXiv
publishDate 2026
record_format arxiv
spellingShingle Si/SiGe multi-channel superlattice structure epitaxial growth with segmented temperature control for Next-Generation Logic Devices
Yao, Wenlong
Li, Zhigang
Bai, Guobin
Gao, Jianfeng
Yu, Jiahan
Li, Junfeng
Wang, Xiaolei
Luo, Jun
Materials Science
Applied Physics
Stacking multiple SiSiGe channels in advanced logic devices faces severe thermal budget accumulation, which degrades interfaces via Ge-Si interdiffusion and strain relaxation.This strategy lowers the Ge diffusion coefficient to 5.6-7% of its value at 650C (Arrhenius estimate), suppressing interdiffusion and preserving pseudomorphic strain. The 4 + 4 channel stack exhibits clear XRD satellite peaks, fully coherent strain state (reciprocal space mapping), sharp interfaces (1.5-2.6 nm transition width) and low RMS roughness (0.08 nm). Quantitative analysis from bottom to top reveals that prolonged high-temperature exposure broadens bottom interfaces and dilutes Ge concentration (from 20% to 18.5%), while the top stack maintains design targets. This work provides a process-physics understanding of thermal budget effects in multi-channel superlattices and establishes a high-quality material foundation for advanced logic devices beyond 2 nm node.
title Si/SiGe multi-channel superlattice structure epitaxial growth with segmented temperature control for Next-Generation Logic Devices
topic Materials Science
Applied Physics
url https://arxiv.org/abs/2605.05667