Cita APA (7a ed.)

Srinath, M., & Hiremath, S. (2022). Verification of Universal Asynchronous Receiver and Transmitter (UART) using System Verilog. Zenodo.

Cita Chicago Style (17a ed.)

Srinath, M., y Sujatha Hiremath. Verification of Universal Asynchronous Receiver and Transmitter (UART) Using System Verilog. Zenodo, 2022.

Cita MLA (9a ed.)

Srinath, M., y Sujatha Hiremath. Verification of Universal Asynchronous Receiver and Transmitter (UART) Using System Verilog. Zenodo, 2022.